One common interface used in computer systems is Peripheral Component Interconnect (PCI) Express (“PCIE” or “PCIe”, e.g., in accordance with PCI Express Base Specification 3.0, Revision 0.5, August 2008). High performance PCIe devices (when used in high-end systems, for example) often are not able to function at their full capacity when performing bus mastering and point-to-point transactions because the intermediate components generally do not have the buffering capacity to provide credits to the devices.
This lack of buffering usually results in high latencies even on high capacity interconnects such as PCIe and QPI (Quick Path Interconnect). This problem is compounded when the transactions have to cross multiple links, for example, in high-end systems and dense systems which support a relatively large amount of I/O (Input/Output) connected to PCIe or QPI.